1. Field of the Invention
The present invention relates generally to a method for producing a DRAM cell including a vertical transistor.
2. Description of the Related Art
In DRAM cell arrangements, that is to say memory cell arrangements with dynamic random access, use is made almost exclusively of so-called single-transistor memory cells. A single-transistor memory cell comprises a read-out transistor and a storage capacitor. The information is stored in the storage capacitor in the form of an electric charge, which represents a logic value, zero or one. By driving the read-out transistor via a word line, this information can be read out via a bit line.
Since the storage density increases from memory generation to memory generation, the required area of the single-transistor memory cell must be reduced from generation to generation. Since limits are imposed on the reduction of the structure sizes by the minimum structure size F which can be produced using the respective technology, this is also associated with an alteration of the single-transistor memory cell. Thus, up until the 1 Mbit generation, both the read-out transistor and the storage capacitor were realized as planar components. Starting with the 4 Mbit memory generation, a further reduction in area had to be effected by means of a three-dimensional arrangement of the read-out transistor and the storage capacitor. One possibility is to realize the storage capacitor in a trench (see, for example K. Yamada et al., A deep trenched capacitor technology for 4 Mbit DRAMs, Proc. Intern. Electronic Devices and Materials IEDM 85, page 702).
Furthermore, it has been proposed (see, for example, Y. Kawamoto et al., A 1,28 .mu.m.sup.2 Bit-Line Shielded Memory Cell Technology for 64 Mbit DRAMs Techn. Digest of VLSI Symposium 1990, page 13) to design the storage capacitor as a so-called stacked capacitor. In this case, a polysilicon structure, for example a crown structure or a cylinder, is formed over the word lines and makes contact with the substrate. This polysilicon structure the storage node. It is provided with a capacitor dielectric and capacitor plate. This concept has the advantage that it is largely compatible with a logic process.
The area for a memory cell of a DRAM belonging to the 1 Gbit generation should only be about 0.2 .mu.m.sup.2. At the same time, the storage capacitor must have a capacitance of 20 to 30 fF. In the case of a cell area such as is available in the 1 Gbit generation, such a capacitance is feasible in a stacked capacitor only with a relatively complicated structure of the polysilicon structure. These complicated structures are more and more difficult to produce, in addition, due to their topology.
Furthermore, it has been proposed to increase the capacitance which can be achieved per area by using a dielectric having a high dielectric constant. Paraelectric and ferroelectric materials, in particular, are suitable as dielectric having a high dielectric constant (see Published PCT application no. WO 93/12542), for example).
The present invention is based on the problem of specifying a method for the production of a DRAM cell arrangement whose memory cells comprise single-transistor memory cells, by means of which method it is possible to achieve the component density which is necessary for the 1 Gbit generation.
This problem is solved by a method for the production of a DRAM cell arrangement.
in which a first mask layer and a second mask layer, which can be etched selectively with respect to one another, are applied to a semiconductor substrate comprising a first layer which is doped by a first conductivity type, a second layer, which is doped by a second conductivity type opposite to the first, and a third layer, which is doped by the first conductivity type and adjoins a main area of the semiconductor substrate,
in which the second mask layer and the first mask layer are structured jointly,
in which the structured first mask layer is etched back under the structured second mask layer by means of selective etching,
in which the structured second mask layer is removed,
in which spacers made of a material which can be etched selectively with respect to the material of the structured first mask layer are formed on the flanks of the structured first mask layer,
in which a third mask layer having essentially conformal edge covering is applied, it having the same etching properties as the first mask layer,
in which the third mask layer is etched back selectively with respect to the spacers until the surface of the spacers is partially exposed,
in which the spacers are removed selectively with respect to the structured first mask layer and with respect to the structured third mask layer,
in which, using the structured first mask layer and the structured third mask layer as an etching mask, first trenches are etched, which first trenches are each in strip form, run essentially parallel and cut through the first layer, the second layer and the third layer,
in which the first trenches are filled with a first insulation structure,
in which second trenches are etched, which second trenches are each in strip form, run essentially parallel, cross the first trenches and reach down into the first layer without cutting through the first layer,
in which the second trenches are provided with a second insulation structure,
in which the width of the second trenches is greater than the width of the first trenches,
in which the first insulation structures and the second insulation structures are etched selectively with respect to the semiconductor material until the surfaces of the structured second layer and third layer are exposed on the flanks of the first trenches and of the second trenches,
in which a gate oxide is formed, which gate oxide covers at least the exposed surface of the second layer,
in which, in order to form gate electrodes, a conductive layer having essentially conformal edge covering is produced, the thickness of which conductive layer is dimensioned such that it fills the first trenches but does not fill the second trenches, and which conductive layer is etched back anisotropically such that conductive spacers are produced on the flanks of the second trenches and the surface of the second insulation structures is partially exposed in the second trenches, while the surface of the first insulation structure in the first trenches remains covered by conductive material,
in which a third insulation structure, which covers the gate electrodes, is produced,
in which storage capacitors are produced which each have a storage node which is electrically connected to the structured third layer. Further refinements of the invention are provided by a method in which the first mask layer and the third mask layer are each formed from SiO.sub.2 and the second mask layer and the spacers are each formed from Si.sub.3 N.sub.4, and the conductive layer is formed from doped polysilicon. Preferably, the semiconductor substrate comprises monocrystalline silicon at least in the region of the main area, and the first layer, the second layer and the third layer are grown on epitaxially. A conductive layer made of CoSi.sub.2, that is grown on expitaxially, is produced under the first layer and is cut through during the etching of the first trenches in one embodiment. In order to form the storage capacitors, a capacitor dielectric and a capacitor plate are applied above the structured third layer, with the result that the structured third layer simultaneously acts as a storage node. The capacitor dielectric may be formed from one of the materials barium strontium titanate, strontium titanate or lead zirconium titanate. The capacitor dielectric may be formed as a continuous layer.
A first mask layer and a second mask layer, which can be etched selectively with respect to one another, are applied to a semiconductor substrate comprising a first layer, which is doped by a first conductivity type, a second layer, which is doped by a second conductivity type opposite to the first, and a third layer, which is doped by the first conductivity type and adjoins a main area of the semiconductor substrate. The second mask layer and the first mask layer are structured jointly.
By selective etching, the structured first mask layer is etched back laterally under the structured second mask layer. The structured second mask layer is subsequently removed.
Spacers made of a material which can be etched selectively with respect to the material of the structured first mask layer are formed on the flanks of the structured first mask layer.
A third mask layer having essentially conformal edge covering is applied, it having the same etching properties as those of the first mask layer. The third mask layer is etched back selectively with respect to the spacers, until the surface of the spacers is partially exposed. The spacers are then removed selectively with respect to the structured first mask layer and with respect to the structured third mask layer.
Using the structured first mask layer and the structured third mask layer as an etching mask, first trenches are etched, which first trenches are each in strip form, run essentially parallel and cut through the first layer, the second layer and the third layer. The first trenches are filled with a first insulation structure.
Second trenches are then etched, which second trenches are each in strip form, run essentially parallel, cross the first trenches and reach down into the first layer without cutting through the first layer. The second trenches are provided with a second insulation structure.
The first insulation structures and the second insulation structures are etched selectively with respect to the semiconductor material, until the surfaces of the structured second layer and third layer are exposed on the flanks of the first trenches and of the second trenches.
A gate oxide which covers at least the exposed surface of the second layer is then formed. A conductive layer having essentially conformal edge covering is subsequently produced for the purpose of forming gate electrodes. The conductive layer is preferably formed from doped polysilicon, since this material can be deposited with good conformity. Alternatively, the conductive layer may be formed from metal silicide or metal, for example tungsten, or from a combination of these materials with doped polysilicon.
The first trenches are produced with a smaller width than the second trenches. The thickness of the conductive layer is dimensioned such that the conductive layer fills the first trenches but does not fill the second trenches. By anisotropically etching back the conductive layer, the surface of the second insulation structure is partially exposed in the second trenches. In the process, doped, conductive spacers remain on the flanks of the second trenches. During this process of anisotropic etching-back, although the conductive material remaining in the first trenches is likewise attacked, the surface of the first insulation structures in the first trenches remains covered with conductive material. In this way, the gate electrodes turn out to be annular structures made of conductive material, in which case that part of the structure which is arranged in each case in the first trenches belongs to two neighbouring gate electrodes and connects the latter to one another in a production-conforming manner.
The gate electrodes are finally covered with a third insulation structure. The third insulation structure essentially completely fills the first trenches and the second trenches above the gate electrodes. In the second trenches, the third insulation structure insulates gate electrodes which are arranged on opposite flanks. The capacitor dielectric and the capacitor plate are subsequently applied. The third insulation structure is preferably produced likewise by depositing a layer having essentially conformal edge covering and etching-back the layer.
For self-aligning production, it is essential that the width of the first trenches and of the second trenches differ such that the conductive layer fills the first trenches but not the second trenches. This makes it possible to structure the gate electrodes, which simultaneously form the word lines, without photolithographic steps. In this method, only two photolithographic steps are required: the structuring of the first mask layer and of the second mask layer and the etching of the second trenches are both carried out each using a lithographically reduced mask. However, these masks are completely non-critical as regards their alignment.
The structured third layer forms a first source/drain region of vertical MOS transistors which in each case constitute the read-out transistors of the single-transistor memory cells of the DRAM cell arrangement. The structured first layer forms buried bit lines and, adjoining the latter, second source/drain regions of the vertical MOS transistors.
Between the first source/drain region and the second source/drain region, the structured second layer forms a channel region which is annularly surrounded by the gate oxide and the gate electrode. The gate electrodes of vertical MOS transistors which are adjacent along a word line adjoin one another and jointly form the word line.
The storage capacitor of the single-transistor memory cells is in each case formed above the main area. This comprises a storage node which is electrically connected to the first source/drain region. The storage node can be designed either in a planar manner or as a polysilicon structure of greater or lesser complexity, as is known from stacked capacitors.
In accordance with one embodiment, a capacitor dielectric is formed on the main area, on the surface of the first source/drain region adjoining the main area, and a capacitor plate is formed over the capacitor dielectric. In this embodiment, the first source/drain region adjoining the main area is additionally used as a storage node for the storage capacitor formed by the capacitor plate, capacitor dielectric and source/drain region. In order to attain a sufficient capacitance given a small area of the storage node, it is advantageous here to use a material having a relative permittivity in the range between 100 and 1000 as the capacitor dielectric.
The DRAM cell arrangement is preferably realized in a semiconductor substrate which comprises monocrystalline silicon at least in the region for the DRAM cell arrangement. That may be either a wafer made of monocrystalline silicon throughout or an SOI (silicon on insulate) substrate, which, on a silicon wafer, comprises an insulating layer and, on the latter, a thin monocrystalline silicon layer.
With the use of the first source/drain region as a storage node, the DRAM cell arrangement according to the invention can be produced with a planar surface or with a surface having a flat topology, thereby making it possible to use a ferroelectric layer or paraelectric layer as the capacitor dielectric. Ferroelectric and paraelectric layers have a high relative permittivity .di-elect cons..sub.r in the range from 500 to 1000. If these layers are deposited by sputtering, they can only be used on planar surfaces or surfaces having a flat topology. Even with CVD (chemical vapor deposition) or sol-gel methods with better edge covering, complicated 3D structures cannot be produced due to the required thickness of the layers. Barium strontium titanate, strontium titanate or lead zirconium titanate is preferably used as the capacitor dielectric. Furthermore, the materials disclosed in published PCT application no. WO 93/12542 are suitable as the capacitor dielectric. With these dielectrics having a high relative permittivity, it is possible to attain the necessary capacitance of 20 to 30 fF even on an area of about 0.1 to 0.4 .mu.m.sup.2.
In the method according to the invention, the first trenches can be produced with a width which is less than the corresponding minimum structure size F which can be produced using the respective technology. If the first mask layer and the second mask layer are structured in strip form with a strip width and a strip spacing of a minimum structure size F, for example 0.25 .mu.m, in the respective technology, the width of the first trenches is less than F/2, since the structured first mask layer is used together with the structured third mask layer as mask and the structure sizes in the structured first mask layer and the structured third mask layer are reduced to below F/2 by the undercutting of the structured first mask layer, the formation of the spacers, the self-aligned formation of the structured third mask layer and the removal of the spacers.
If the width of the second trenches is also a minimum structure size F, for example 0.25 .mu.m, in the respective technology, then the DRAM cell arrangement can be produced with a space requirement per memory cell of 2F.sup.2.
It lies within the scope of the invention to grow on epitaxially the regions for the source/drain regions and the channel region as well as the bit lines as whole-area layers. In this case, it is possible, given the use of a substrate which comprises monocrystalline silicon in the region of the DRAM cell arrangement, to produce a conductive layer made of CoSi.sub.2 l grown on epitaxially, for the purpose of improving the conductivity of the bit lines under the second source/drain regions. This conductive layer is likewise cut through during the etching of the first trenches and is a component part of the bit lines.